LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH

Atomic bit clear on halfword

This instruction atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

If the destination register is not WZR, LDCLRAH and LDCLRALH load from memory with acquire semantics.
LDCLRLH and LDCLRALH store to memory with release semantics.
LDCLRH has neither acquire nor release semantics.

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

This instruction is used by the alias STCLRH, STCLRLH.

Integer class

(FEAT_LSE)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	1	1	0	0	0	A	R	1	Rs					0	0	0	1	0	0	Rn					Rt
size					VR											o3	opc

No memory ordering encoding

(A == 0 && R == 0)

LDCLRH <Ws>, <Wt>, [<Xn|SP>]

Acquire encoding

(A == 1 && R == 0)

LDCLRAH <Ws>, <Wt>, [<Xn|SP>]

Acquire-release encoding

(A == 1 && R == 1)

LDCLRALH <Ws>, <Wt>, [<Xn|SP>]

Release encoding

(A == 0 && R == 1)

LDCLRLH <Ws>, <Wt>, [<Xn|SP>]

Decode (all encodings)

if !IsFeatureImplemented(FEAT_LSE) then EndOfDecode(Decode_UNDEF); constant integer s = UInt(Rs); constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant boolean acquire = A == '1' && Rt != '11111'; constant boolean release = R == '1'; constant boolean tagchecked = n != 31;

Assembler Symbols

<Ws>	Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Wt>	Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Alias Conditions

Alias	Is preferred when
STCLRH, STCLRLH	A == '0' && Rt == '11111'

Operation

bits(64) address; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_BIC, acquire, release, tagchecked, privileged, t, s); if n == 31 then CheckSPAlignment(); address = SP[64]; else address = X[n, 64]; constant bits(16) comparevalue = bits(16) UNKNOWN; // Irrelevant when not executing CAS constant bits(16) value = X[s, 16]; constant bits(16) data = MemAtomic(address, comparevalue, value, accdesc); if t != 31 then X[t, 32] = ZeroExtend(data, 32);

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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