Single-copy atomic 64-byte load-acquire
This instruction derives an address from a base register value, loads eight 64-bit doublewords from a memory location, and writes them to consecutive registers. The load starts at register Xt, with the data being read as X(t+7)::X(t+6)::X(t+5)::X(t+4)::X(t+3)::X(t+2)::X(t+1)::Xt = Data[511:0]. The data is loaded atomically and is required to be 64-byte aligned.
It is IMPLEMENTATION DEFINED which memory locations support this instruction. A memory location that supports LDA64B also supports LD64B, ST64B, and STL64B.
LDA64B loads from memory with acquire semantics.
For more information, including about the memory types accessible and how the accesses are performed, see Single-copy atomic 64-byte load/store.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | Rn | Rt | ||||||||
| size | VR | A | R | Rs | o3 | opc | |||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LSC64B) then EndOfDecode(Decode_UNDEF); end; if !IsFeatureImplemented(FEAT_LS64) then EndOfDecode(Decode_UNDEF); end; if Rt[4:3] == '11' || Rt[0] == '1' then EndOfDecode(Decode_UNDEF); end; let withstatus : boolean = FALSE; let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let tagchecked : boolean = n != 31; let acqrel : boolean = TRUE;
LDA64B has the same CONSTRAINED UNPREDICTABLE behavior as LD64B. For information about this CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LD64B.
| <Xt> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
CheckLDST64BEnabled(acqrel); var data : bits(512); var address : bits(64); var value : bits(64); let accdesc : AccessDescriptor = CreateAccDescLS64(MemOp_LOAD, withstatus, acqrel, tagchecked); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; data = MemLoad64B(address, accdesc); for i = 0 to 7 do value = data[63+64*i : 64*i]; if BigEndian(accdesc.acctype) then value = BigEndianReverse{64}(value); end; X{64}(t+i) = value; end;
Version 2026.09 — Copyright © 2010-2026 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.