Gather load unsigned halfwords to vector (vector index)
Gather load of unsigned halfwords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 2. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 6 classes: 32-bit scaled offset , 32-bit unpacked scaled offset , 32-bit unpacked unscaled offset , 32-bit unscaled offset , 64-bit scaled offset and 64-bit unscaled offset
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| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | xs | 1 | Zm | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| U | ff | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 16; constant integer offs_size = 32; constant boolean unsigned = TRUE; constant boolean offs_unsigned = xs == '0'; constant integer scale = 1;
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| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | xs | 1 | Zm | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| opc | U | ff | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant integer offs_size = 32; constant boolean unsigned = TRUE; constant boolean offs_unsigned = xs == '0'; constant integer scale = 1;
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| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | xs | 0 | Zm | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| msz | U | ff | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant integer offs_size = 32; constant boolean unsigned = TRUE; constant boolean offs_unsigned = xs == '0'; constant integer scale = 0;
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| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | xs | 0 | Zm | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| opc | U | ff | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 16; constant integer offs_size = 32; constant boolean unsigned = TRUE; constant boolean offs_unsigned = xs == '0'; constant integer scale = 0;
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| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | Zm | 1 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| opc | U | ff | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant integer offs_size = 64; constant boolean unsigned = TRUE; constant boolean offs_unsigned = TRUE; constant integer scale = 1;
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| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | Zm | 1 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| msz | U | ff | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant integer offs_size = 64; constant boolean unsigned = TRUE; constant boolean offs_unsigned = TRUE; constant integer scale = 0;
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Zm> |
Is the name of the offset scalable vector register, encoded in the "Zm" field. |
| <mod> |
Is the index extend and shift specifier,
encoded in
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CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(VL) offset; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; constant boolean contiguous = FALSE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[64] else X[n, 64]; offset = Z[m, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned); constant bits(64) addr = AddressAdd(base, off << scale, accdesc); data = Mem[addr, mbytes, accdesc]; Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(esize); Z[t, VL] = result;