Contiguous load of halfwords to multiple consecutive vectors (scalar index)
This instruction performs a contiguous load of unsigned halfwords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index that is added to the base address. After each element access the index value is incremented, but the index register is not updated.
Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
It has encodings from 2 classes: Two registers and Four registers
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rm | 0 | 0 | 1 | PNg | Rn | Zt | 0 | |||||||||||||
| msz | N | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt('1':PNg); constant integer nreg = 2; constant integer t = UInt(Zt:'0'); constant integer esize = 16;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rm | 1 | 0 | 1 | PNg | Rn | Zt | 0 | 0 | ||||||||||||
| msz | N | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt('1':PNg); constant integer nreg = 4; constant integer t = UInt(Zt:'00'); constant integer esize = 16;
| <Zt2> |
Is the name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1. |
| <PNg> |
Is the name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
| <Zt4> |
Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3. |
if IsFeatureImplemented(FEAT_SVE2p1) then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant integer mbytes = esize DIV 8; bits(64) offset; bits(64) base; bits(64) addr; constant bits(PL) pred = P[g, PL]; constant bits(PL * nreg) mask = CounterToPredicate(pred<15:0>, PL * nreg); array [0..3] of bits(VL) values; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant integer transfer = t; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[64] else X[n, 64]; offset = X[m, 64]; addr = AddressAdd(base, UInt(offset) * mbytes, accdesc); for r = 0 to nreg-1 for e = 0 to elements-1 if ActivePredicateElement(mask, r * elements + e, esize) then Elem[values[r], e, esize] = Mem[addr, mbytes, accdesc]; else Elem[values[r], e, esize] = Zeros(esize); addr = AddressIncrement(addr, mbytes, accdesc); for r = 0 to nreg-1 Z[transfer+r, VL] = values[r];
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
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