LASTA (scalar)

Extract element after last to general-purpose register

This instruction extracts the element after the Last active element to a general-purpose register. If there is an Active element, the element after the Last active element modulo the number of elements from the final source vector register is extracted. If there are no Active elements, element zero is extracted. Then the extracted element is zero-extended and placed in the destination general-purpose register.

SVE class

(FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1	size		1	0	0	0	0	0	1	0	1	Pg			Zn					Rd
															B

Encoding

LASTA <R><d>, <Pg>, <Zn>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer rsize = if esize < 64 then 32 else 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Rd); constant boolean isBefore = FALSE;

Assembler Symbols

<R>

Is a width specifier, encoded in size:

size	<R>
00	W
01	W
10	W
11	X

<d>	Is the number [0-30] of the destination general-purpose register or the name ZR (31), encoded in the "Rd" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>	Is the name of the source scalable vector register, encoded in the "Zn" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = Z[n, VL]; bits(rsize) result; integer last = LastActiveElement(mask, esize); if isBefore then if last < 0 then last = elements - 1; else last = last + 1; if last >= elements then last = 0; result = ZeroExtend(Elem[operand, last, esize], rsize); X[d, rsize] = result;

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.

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