Insert SIMD&FP scalar register in shifted vector
Shift the destination vector left by one element, and then place a copy of the SIMD&FP scalar register in element 0 of the destination vector. This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Vm | Zdn | |||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer dn = UInt(Zdn); constant integer m = UInt(Vm);
| <Zdn> |
Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. |
| <T> |
Is the size specifier,
encoded in
|
| <V> |
Is a width specifier,
encoded in
|
| <m> |
Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant bits(VL) dest = Z[dn, VL]; constant bits(esize) src = V[m, esize]; Z[dn, VL] = dest<(VL-esize)-1:0> : src;