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FRINTA

Multi-vector floating-point round to integral value, to nearest with ties away from zero

This instruction rounds each element of the two or four source vectors to the nearest integral floating-point value, with ties rounding away from zero, and places the results in the corresponding elements of the two or four destination vectors.

This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.

This instruction is unpredicated.

It has encodings from 2 classes: Two registers and Four registers

Two registers

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000110101100111000Zn0Zd0
sizeopc

Encoding

FRINTA { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd:'0'); constant integer nreg = 2; constant boolean exact = FALSE; constant FPRounding rounding = FPRounding_TIEAWAY;

Four registers

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000110111100111000Zn00Zd00
sizeopc

Encoding

FRINTA { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd:'00'); constant integer nreg = 4; constant boolean exact = FALSE; constant FPRounding rounding = FPRounding_TIEAWAY;

Assembler Symbols

<Zd1>

For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn1>

For the "Two registers" variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.

<Zn2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zd4>

Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

<Zn4>

Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.

Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; array [0..3] of bits(VL) results; for r = 0 to nreg-1 constant bits(VL) operand = Z[n+r, VL]; for e = 0 to elements-1 constant bits(32) element = Elem[operand, e, 32]; Elem[results[r], e, 32] = FPRoundInt(element, FPCR, rounding, exact); for r = 0 to nreg-1 Z[d+r, VL] = results[r];