FMMLA (non-widening)

Half-precision matrix multiply-accumulate

This instruction multiplies the 2x2 matrix of half-precision values in each 64-bit segment of the first source vector by the 2x2 matrix of half-precision values in the corresponding 64-bit segment of the second source vector. The intermediate products are rounded before they are summed, and the intermediate sum is rounded before accumulation into the 2x2 half-precision matrix held in the corresponding 64-bit segment of the addend and destination vector. This is equivalent to performing a 2-way dot product per destination element.

Advanced SIMD class

(FEAT_F16MM)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	1	1	1	0	1	1	0	Rm					1	1	1	0	1	1	Rn					Rd
	Q	U						size									opcode

Encoding

FMMLA <Vd>.8H, <Vn>.8H, <Vm>.8H

Decode

if !IsFeatureImplemented(FEAT_F16MM) then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm);

Assembler Symbols

<Vd>	Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.

<Vn>	Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>	Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); constant bits(128) operand1 = V[n, 128]; constant bits(128) operand2 = V[m, 128]; constant bits(128) operand3 = V[d, 128]; bits(128) result; for s = 0 to 1 constant bits(64) op1 = Elem[operand1, s, 64]; constant bits(64) op2 = Elem[operand2, s, 64]; constant bits(64) acc = Elem[operand3, s, 64]; Elem[result, s, 64] = FPMatMulAdd(acc, op1, op2, 16, FPCR); V[d, 128] = result;