Floating-point narrowing convert to interleaved unsigned integer, rounding toward zero
This instruction converts each floating-point element of the pair of source vectors to half-width unsigned integer nearer to zero, and places the two-way interleaved results in the corresponding half-width elements of the destination vector.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | Zn | 0 | Zd | ||||||||
| U | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p3) && !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); if size == '00' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd); constant boolean unsigned = TRUE; constant FPRounding rounding = FPRounding_ZERO;
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. |
| <Tb> |
Is the size specifier,
encoded in
|
| <Zn2> |
Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[n+0, VL]; constant bits(VL) operand2 = Z[n+1, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(esize) element1 = Elem[operand1, e, esize]; constant bits(esize) element2 = Elem[operand2, e, esize]; Elem[result, 2*e + 0, esize DIV 2] = FPToFixed(element1, 0, unsigned, FPCR, rounding, esize DIV 2); Elem[result, 2*e + 1, esize DIV 2] = FPToFixed(element2, 0, unsigned, FPCR, rounding, esize DIV 2); Z[d, VL] = result;
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