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FCMP

Floating-point quiet compare (scalar)

This instruction compares the two SIMD&FP source register values, or the first SIMD&FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags.

This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
00011110ftype1Rm001000Rn0x000
MSopopc

Encoding for the Half-precision variant

(FEAT_FP16)

Applies when (ftype == 11 && opc == 00)

FCMP <Hn>, <Hm>

Encoding for the Half-precision, zero variant

(FEAT_FP16)

Applies when (ftype == 11 && Rm == (00000) && opc == 01)

FCMP <Hn>, #0.0

Encoding for the Single-precision variant

(FEAT_FP)

Applies when (ftype == 00 && opc == 00)

FCMP <Sn>, <Sm>

Encoding for the Single-precision, zero variant

(FEAT_FP)

Applies when (ftype == 00 && Rm == (00000) && opc == 01)

FCMP <Sn>, #0.0

Encoding for the Double-precision variant

(FEAT_FP)

Applies when (ftype == 01 && opc == 00)

FCMP <Dn>, <Dm>

Encoding for the Double-precision, zero variant

(FEAT_FP)

Applies when (ftype == 01 && Rm == (00000) && opc == 01)

FCMP <Dn>, #0.0

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); if ftype == '10' then EndOfDecode(Decode_UNDEF); if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Rn); constant integer m = UInt(Rm); // ignored when opc<0> == '1' constant integer datasize = 8 << UInt(ftype EOR '10'); constant boolean signal_all_nans = FALSE; constant boolean cmp_with_zero = (opc<0> == '1');

Assembler Symbols

<Hn>

For the "Half-precision" variant: is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

For the "Half-precision, zero" variant: is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Hm>

Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<Sn>

For the "Single-precision" variant: is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

For the "Single-precision, zero" variant: is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Sm>

Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<Dn>

For the "Double-precision" variant: is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

For the "Double-precision, zero" variant: is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPEnabled64(); constant bits(datasize) operand1 = V[n, datasize]; constant bits(datasize) operand2 = if cmp_with_zero then FPZero('0', datasize) else V[m, datasize]; PSTATE.<N,Z,C,V> = FPCompare(operand1, operand2, signal_all_nans, FPCR);