Floating-point conditional signaling compare (scalar)
This instruction compares the two SIMD&FP source register values and writes the result to the PSTATE.{N, Z, C, V} flags. If the condition does not pass, then the PSTATE.{N, Z, C, V} flags are set to the flag bit specifier.
This instruction raises an Invalid Operation floating-point exception if either or both of the operands is any type of NaN.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | Rm | cond | 0 | 1 | Rn | 1 | nzcv | |||||||||||||||
| M | S | op | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); if ftype == '10' then EndOfDecode(Decode_UNDEF); if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer datasize = 8 << UInt(ftype EOR '10'); constant bits(4) condition = cond; bits(4) flags = nzcv;
| <Hn> |
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Hm> |
Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
| <nzcv> |
Is the flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field. |
| <Sn> |
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Sm> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPEnabled64(); constant bits(datasize) operand1 = V[n, datasize]; constant bits(datasize) operand2 = V[m, datasize]; if ConditionHolds(condition) then constant boolean signal_all_nans = TRUE; flags = FPCompare(operand1, operand2, signal_all_nans, FPCR); PSTATE.<N,Z,C,V> = flags;