CLASTB (scalar)

Conditionally extract last element to general-purpose register

This instruction extracts, from the source vector register, the Last active element, and then zero-extends that element to destructively place in the destination and first source general-purpose register. If there are no Active elements, the least significant element-size bits of the destination and first source general-purpose register are destructively zero-extended.

SVE class

(FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1	size		1	1	0	0	0	1	1	0	1	Pg			Zm					Rdn
															B

Encoding

CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer dn = UInt(Rdn); constant integer m = UInt(Zm); constant integer csize = if esize < 64 then 32 else 64; constant boolean isBefore = TRUE;

Assembler Symbols

<R>

Is a width specifier, encoded in size:

size	<R>
00	W
01	W
10	W
11	X

<dn>	Is the number [0-30] of the source and destination general-purpose register or the name ZR (31), encoded in the "Rdn" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zm>	Is the name of the source scalable vector register, encoded in the "Zm" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(esize) operand1 = X[dn, esize]; constant bits(VL) operand2 = Z[m, VL]; bits(csize) result; integer last = LastActiveElement(mask, esize); if last < 0 then result = ZeroExtend(operand1, csize); else if !isBefore then last = last + 1; if last >= elements then last = 0; result = ZeroExtend(Elem[operand2, last, esize], csize); X[dn, csize] = result;

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.

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