CFLT<cc> (immediate)

Compare register with immediate and fault

This instruction compares the value in a register with an immediate, and generates a Conditional fault exception if the comparison is true. If an exception is generated, the <reason> operand is copied to ESR_ELx.

This instruction does not affect the condition flags.

This instruction is used by the pseudo-instructions CFLTGE (immediate), CFLTHS (immediate), CFLTLE (immediate), CFLTLS (immediate), CFLTNZ, and CFLTZ.

Fault class

(FEAT_CFLT)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
sf	1	1	1	0	1	1	0	cc			imm9h					0	0	0	0	imm2		0	imm9l				Rt

32-bit greater than encoding

(sf == 0 && cc == 000)

CFLTGT #<reason>, <Wt>, #<imm>

32-bit less than encoding

(sf == 0 && cc == 001)

CFLTLT #<reason>, <Wt>, #<imm>

32-bit higher encoding

(sf == 0 && cc == 010)

CFLTHI #<reason>, <Wt>, #<imm>

32-bit lower encoding

(sf == 0 && cc == 011)

CFLTLO #<reason>, <Wt>, #<imm>

32-bit equal encoding

(sf == 0 && cc == 100)

CFLTEQ #<reason>, <Wt>, #<imm>

32-bit not equal encoding

(sf == 0 && cc == 101)

CFLTNE #<reason>, <Wt>, #<imm>

64-bit greater than encoding

(sf == 1 && cc == 000)

CFLTGT #<reason>, <Xt>, #<imm>

64-bit less than encoding

(sf == 1 && cc == 001)

CFLTLT #<reason>, <Xt>, #<imm>

64-bit higher encoding

(sf == 1 && cc == 010)

CFLTHI #<reason>, <Xt>, #<imm>

64-bit lower encoding

(sf == 1 && cc == 011)

CFLTLO #<reason>, <Xt>, #<imm>

64-bit equal encoding

(sf == 1 && cc == 100)

CFLTEQ #<reason>, <Xt>, #<imm>

64-bit not equal encoding

(sf == 1 && cc == 101)

CFLTNE #<reason>, <Xt>, #<imm>

Decode (all encodings)

if !IsFeatureImplemented(FEAT_CFLT) then EndOfDecode(Decode_UNDEF); end; let datasize : integer{} = 32 << UInt(sf); let t : integer = UInt(Rt); let imm : bits(9) = imm9h::imm9l; let reason : bits(16) = ZeroExtend{}(imm2); var cmp : CmpOp; var unsigned : boolean; case cc of when '000' => cmp = Cmp_GT; unsigned = FALSE; when '001' => cmp = Cmp_LT; unsigned = FALSE; when '010' => cmp = Cmp_GT; unsigned = TRUE; when '011' => cmp = Cmp_LT; unsigned = TRUE; when '100' => cmp = Cmp_EQ; unsigned = FALSE; when '101' => cmp = Cmp_NE; unsigned = FALSE; otherwise => EndOfDecode(Decode_UNDEF); end;

Assembler Symbols

Is a 2-bit unsigned immediate, in the range 0 to 3, encoded in the "imm2" field.

<Wt>	Is the 32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

<imm>	For the "32-bit equal", "32-bit greater than", "32-bit less than", "32-bit not equal", "64-bit equal", "64-bit greater than", "64-bit less than", and "64-bit not equal" variants: is a signed immediate, in the range -256 to 255, encoded in "imm9h:imm9l".
	For the "32-bit higher", "32-bit lower", "64-bit higher", and "64-bit lower" variants: is an unsigned immediate, in the range 0 to 511, encoded in "imm9h:imm9l".

<Xt>	Is the 64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

Operation

CheckCFLTEnabled(); let operand1 : bits(datasize) = X{}(t); var cond : boolean; let value1 : integer = if unsigned then UInt(operand1) else SInt(operand1); let value2 : integer = if unsigned then UInt(imm) else SInt(imm); case cmp of when Cmp_EQ => cond = value1 == value2; when Cmp_NE => cond = value1 != value2; when Cmp_LT => cond = value1 < value2; when Cmp_GT => cond = value1 > value2; end; if cond then let isflt : boolean = FALSE; AArch64_ConditionalFault(isflt, reason); end;

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