BFloat16 matrix multiply-accumulate
This instruction multiplies the 2x2 matrix of BFloat16 values in each 64-bit segment of the first source vector by the 2x2 matrix of BFloat16 values in the corresponding 64-bit segment of the second source vector. The intermediate products are rounded before they are summed, and the intermediate sum is rounded before accumulation into the 2x2 BFloat16 matrix held in the corresponding 64-bit segment of the addend and destination vector. This is equivalent to performing a 2-way dot product per destination element. This instruction is unpredicated.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | Zm | 1 | 1 | 1 | 0 | 0 | 0 | Zn | Zda | ||||||||||||
| op | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE_B16MM) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda);
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer segments = VL DIV 64; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; constant bits(VL) operand3 = Z[da, VL]; bits(VL) result; bits(64) op1, op2; bits(64) res, addend; for s = 0 to segments-1 op1 = Elem[operand1, s, 64]; op2 = Elem[operand2, s, 64]; addend = Elem[operand3, s, 64]; res = BFMatMulAdd(addend, op1, op2, FPCR); Elem[result, s, 64] = res; Z[da, VL] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:
Version 2025.09 — Copyright © 2010-2025 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.