BFC

Bitfield clear

This instruction sets a bitfield of <width> bits at bit position <lsb> of the destination register to zero, leaving the other destination bits unchanged.

This is an alias of BFM. This means:

The encodings in this description are named to match the encodings of BFM.
The description of BFM gives the operational pseudocode, any constrained unpredictable behavior, and any operational information for this instruction.

Leaving other bits unchanged class

(FEAT_ASMv8p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
sf	0	1	1	0	0	1	1	0	N	immr						imms						1	1	1	1	1	Rd
	opc																					Rn

32-bit encoding

(sf == 0 && N == 0)

BFC <Wd>, #<lsb>, #<width>

is equivalent to

BFM <Wd>, WZR, #(-<lsb> MOD 32), #(<width>-1)

and is the preferred disassembly when UInt(imms) < UInt(immr).

64-bit encoding

(sf == 1 && N == 1)

BFC <Xd>, #<lsb>, #<width>

is equivalent to

BFM <Xd>, XZR, #(-<lsb> MOD 64), #(<width>-1)

and is the preferred disassembly when UInt(imms) < UInt(immr).

Assembler Symbols

<Wd>	Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<lsb>	For the "32-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 31.
	For the "64-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 63.

<width>	For the "32-bit" variant: is the width of the bitfield, in the range 1 to 32-<lsb>.
	For the "64-bit" variant: is the width of the bitfield, in the range 1 to 64-<lsb>.

<Xd>	Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

Operation

The description of BFM gives the operational pseudocode for this instruction.

Operational Information

The description of BFM gives the operational information for this instruction.

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