Gather lower bits from positions selected by bitmask
This instruction gathers bits in each element of the first source vector from the bit positions indicated by nonzero bits in the corresponding mask element of the second source vector to the lowest-numbered contiguous bits of the corresponding destination element, preserving their order, and sets the remaining higher-numbered bits to zero. This instruction is unpredicated.
ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SSVE_BitPerm is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | size | 0 | Zm | 1 | 0 | 1 | 1 | 0 | 0 | Zn | Zd | |||||||||||||
| opc | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE_BitPerm) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
if IsFeatureImplemented(FEAT_SSVE_BitPerm) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let data : bits(VL) = Z{}(n); let mask : bits(VL) = Z{}(m); var result : bits(VL); for e = 0 to elements - 1 do result[e*:esize] = BitExtract{esize}(data[e*:esize], mask[e*:esize]); end; Z{VL}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
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