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BCAX

Bitwise clear and exclusive-OR

Bitwise AND elements of the second source vector with the corresponding inverted elements of the third source vector, then exclusive-OR the results with corresponding elements of the first source vector. The final results are destructively placed in the corresponding elements of the destination and first source vector. This instruction is unpredicated.

SVE2

(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000100011Zm001110ZkZdn
opco2

Encoding

BCAX <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); constant integer m = UInt(Zm); constant integer k = UInt(Zk); constant integer dn = UInt(Zdn);

Assembler Symbols

<Zdn>

Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<Zk>

Is the name of the third source scalable vector register, encoded in the "Zk" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = Z[m, VL]; constant bits(VL) operand3 = Z[k, VL]; Z[dn, VL] = operand1 EOR (operand2 AND NOT(operand3));