AESMC

AES mix columns

This instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the MixColumns() transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.

ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.

This instruction is legal when executed in Streaming SVE mode if one of the following is true:

Both FEAT_SSVE_AES and FEAT_SVE_AES are implemented.
FEAT_SME_FA64 is implemented and enabled.

SVE2 class

(FEAT_SVE_AES)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	1	0	0	1	0	0	0	0	0	1	1	1	0	0	0	0	0	0	0	0	Zdn
								size													op

Encoding

AESMC <Zdn>.B, <Zdn>.B

Decode

if !IsFeatureImplemented(FEAT_SVE_AES) then EndOfDecode(Decode_UNDEF); constant integer dn = UInt(Zdn);

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

Operation

if IsFeatureImplemented(FEAT_SSVE_AES) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer segments = VL DIV 128; constant bits(VL) operand = Z[dn, VL]; bits(VL) result; for s = 0 to segments-1 Elem[result, s, 128] = AESMixColumns(Elem[operand, s, 128]); Z[dn, VL] = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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