Add pairwise within quadword vector segments (unpredicated)
This instruction adds pairs of adjacent elements within each concatenated pair of 128-bit segments of the first and second source vectors, and places the results in the corresponding 128-bit segment of the destination vector.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | 1 | Zm | 0 | 1 | 1 | 1 | 1 | 0 | Zn | Zd | |||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p3) && !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer segments = VL DIV 128; constant integer elempersegment = 128 DIV esize; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; bits(VL) result; for s = 0 to segments-1 constant bits(128) seg1 = Elem[operand1, s, 128]; constant bits(128) seg2 = Elem[operand2, s, 128]; constant bits(256) concat = seg2:seg1; for e = 0 to elempersegment-1 constant bits(esize) element1 = Elem[concat, 2*e + 0, esize]; constant bits(esize) element2 = Elem[concat, 2*e + 1, esize]; Elem[result, s*elempersegment + e, esize] = element1 + element2; Z[d, VL] = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
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