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PMZR_EL0: Performance Monitors Zero with Mask

Purpose

Zero the set of counters specified by the mask written to PMZR_EL0.

Configuration

External register PMZR_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMZR_EL0[63:0].

This register is present only when FEAT_PMUv3_EXT64 is implemented and FEAT_PMUv3p9 is implemented. Otherwise, direct accesses to PMZR_EL0 are RES0.

PMZR_EL0 is in the Core power domain.

Attributes

PMZR_EL0 is a 64-bit register.

This register is part of the PMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0F0
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

Bits [63:33]

Reserved, RES0.

F<m>, bit [m+32], for m = 0

When FEAT_PMUv3_ICNTR is implemented:

Zero fixed-function counter <m>.

F<m>Meaning
0b0

Write is ignored.

0b1

Set fixed-function counter <m> to zero.

Writing 1 to PMZR_EL0.F0 sets PMU.PMICNTR_EL0 to zero.



Otherwise:

Reserved, RES0.

C, bit [31]

Zero PMU.PMCCNTR_EL0.

CMeaning
0b0

Write is ignored.

0b1

Set PMU.PMCCNTR_EL0 to zero.

P<m>, bit [m], for m = 30 to 0

Zero PMEVCNTR<m>_EL0.

P<m>Meaning
0b0

Write is ignored.

0b1

Set PMEVCNTR<m>_EL0 to zero.

Accessing this field has the following behavior:

Accessing PMZR_EL0

Accesses to this register use the following encodings:

Accessible at offset 0xCA0 from PMU