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PMSSCR_EL1: Performance Monitors Snapshot Status and Capture Register

Purpose

Holds status information about the captured counters and provides a mechanism for software to initiate a sample.

Configuration

This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMSSCR_EL1 are RES0.

Attributes

PMSSCR_EL1 is a 64-bit register.

This register is part of the PMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0NC
RES0SS

Bits [63:33]

Reserved, RES0.

NC, bit [32]

No Capture. Indicates whether the PMU counters have been captured.

NCMeaning
0b0

PMU counters captured.

0b1

PMU counters not captured.

The reset behavior of this field is:

Bits [31:1]

Reserved, RES0.

SS, bit [0]

Snapshot Capture and Status.

SSMeaning
0b0

On a read, the Capture event has completed.

0b1

On a read, the Capture event has not completed.

On a write, request a Capture event.

A write of 0 to this field is ignored.

It is CONSTRAINED UNPREDICTABLE whether a Capture event has completed if this field is modified when the Capture event is ongoing.

The reset behavior of this field is:

Accessing this field has the following behavior:

Accessing PMSSCR_EL1

Accesses to this register use the following encodings:

Accessible at offset 0xE30 from PMU