← Home

PMOVSSET_EL0: Performance Monitors Overflow Flag Status Set Register

Purpose

Allows software to set the unsigned overflow flags for the following counters to 1:

Reading from this register shows the current unsigned overflow flag values.

Configuration

External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMOVSSET_EL0[31:0] when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is not implemented.

External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMOVSCLR_EL0[31:0] when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is not implemented.

External register PMOVSSET_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMOVSSET_EL0[63:32] when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented.

External register PMOVSSET_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMOVSCLR_EL0[63:32] when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented.

External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSR[31:0].

External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSSET[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMOVSSET_EL0 are RES0.

PMOVSSET_EL0 is in the Core power domain.

Attributes

PMOVSSET_EL0 is a:

This register is part of the PMU block.

Field descriptions

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0F0
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

Bits [63:33]

Reserved, RES0.

F0, bit [32]

When FEAT_PMUv3_ICNTR is implemented:

Unsigned overflow flag for PMU.PMICNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMU.PMICNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMU.PMICNTR_EL0.

F0Meaning
0b0

PMU.PMICNTR_EL0 has not overflowed.

0b1

PMU.PMICNTR_EL0 has overflowed.

The reset behavior of this field is:

Accessing this field has the following behavior:



Otherwise:

Reserved, RES0.

C, bit [31]

Unsigned overflow flag for PMU.PMCCNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMU.PMCCNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMU.PMCCNTR_EL0 overflow status.

CMeaning
0b0

PMU.PMCCNTR_EL0 has not overflowed.

0b1

PMU.PMCCNTR_EL0 has overflowed.

PMU.PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMU.PMCCNTR_EL0[31:0] or unsigned overflow of PMU.PMCCNTR_EL0[63:0].

The reset behavior of this field is:

Accessing this field has the following behavior:

P<m>, bit [m], for m = 30 to 0

Unsigned overflow flag for PMU.PMEVCNTR<m>_EL0 set. On writes, allows software to set the unsigned overflow flag for PMU.PMEVCNTR<m>_EL0 to 1. On reads, returns the unsigned overflow flag for PMU.PMEVCNTR<m>_EL0 overflow status.

P<m>Meaning
0b0

PMU.PMEVCNTR<m>_EL0 has not overflowed.

0b1

PMU.PMEVCNTR<m>_EL0 has overflowed.

If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMU.PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMU.PMEVCNTR<n>_EL0[31:0] or unsigned overflow of PMU.PMEVCNTR<n>_EL0[63:0].

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

313029282726252423222120191817161514131211109876543210
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

C, bit [31]

Unsigned overflow flag for PMU.PMCCNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMU.PMCCNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMU.PMCCNTR_EL0 overflow status.

CMeaning
0b0

PMU.PMCCNTR_EL0 has not overflowed.

0b1

PMU.PMCCNTR_EL0 has overflowed.

PMU.PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMU.PMCCNTR_EL0[31:0] or unsigned overflow of PMU.PMCCNTR_EL0[63:0].

The reset behavior of this field is:

Accessing this field has the following behavior:

P<m>, bit [m], for m = 30 to 0

Unsigned overflow flag for PMU.PMEVCNTR<m>_EL0 set. On writes, allows software to set the unsigned overflow flag for PMU.PMEVCNTR<m>_EL0 to 1. On reads, returns the unsigned overflow flag for PMU.PMEVCNTR<m>_EL0 overflow status.

P<m>Meaning
0b0

PMU.PMEVCNTR<m>_EL0 has not overflowed.

0b1

PMU.PMEVCNTR<m>_EL0 has overflowed.

If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMU.PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMU.PMEVCNTR<n>_EL0[31:0] or unsigned overflow of PMU.PMEVCNTR<n>_EL0[63:0].

The reset behavior of this field is:

Accessing this field has the following behavior:

Accessing PMOVSSET_EL0

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings:

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3_ICNTR is implemented or FEAT_PMUv3p9 is implemented

[63:0] Accessible at offset 0xCC0 from PMU

When FEAT_PMUv3_EXT32 is implemented, FEAT_PMUv3_ICNTR is not implemented and FEAT_PMUv3p9 is not implemented

[31:0] Accessible at offset 0xCC0 from PMU