The unsigned overflow flags for the Cycle Count Register, PMU.PMCCNTR_EL0, and each of the implemented event counters PMEVCNTR<n>.
External register PMOVS bits [63:0] are architecturally mapped to AArch64 System register PMOVSSET_EL0[63:0].
External register PMOVS bits [63:0] are architecturally mapped to AArch64 System register PMOVSCLR_EL0[63:0].
External register PMOVS bits [31:0] are architecturally mapped to AArch32 System register PMOVSSET[31:0].
External register PMOVS bits [31:0] are architecturally mapped to AArch32 System register PMOVSR[31:0].
This register is present only when FEAT_PMUv3_EXT64 is implemented. Otherwise, direct accesses to PMOVS are RES0.
PMOVS is a 64-bit register.
This register is part of the PMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | F0 | ||||||||||||||||||||||||||||||
| C | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Reserved, RES0.
PMU.PMICNTR_EL0 unsigned overflow flag.
| F0 | Meaning |
|---|---|
| 0b0 |
PMU.PMICNTR_EL0 has not overflowed. |
| 0b1 |
PMU.PMICNTR_EL0 has overflowed. |
The reset behavior of this field is:
Reserved, RES0.
Cycle counter unsigned overflow flag.
| C | Meaning |
|---|---|
| 0b0 |
The cycle counter has not overflowed since this bit was last cleared. |
| 0b1 |
The cycle counter has overflowed since this bit was last cleared. |
PMU.PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMU.PMCCNTR_EL0[31:0] or unsigned overflow of PMU.PMCCNTR_EL0[63:0].
The reset behavior of this field is:
Event counter unsigned overflow bit for PMU.PMEVCNTR<n>_EL0.
If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.
| P<n> | Meaning |
|---|---|
| 0b0 |
PMU.PMEVCNTR<n>_EL0 has not overflowed since this bit was last cleared. |
| 0b1 |
PMU.PMEVCNTR<n>_EL0 has overflowed since this bit was last cleared. |
If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMU.PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMU.PMEVCNTR<n>_EL0[31:0] or unsigned overflow of PMU.PMEVCNTR<n>_EL0[63:0].
The reset behavior of this field is:
Accesses to this register use the following encodings:
Accessible at offset 0xC90 from PMU