Indicates the current status of the software lock for Performance Monitors registers.
The optional Software Lock provides a lock to prevent memory-mapped writes to the Performance Monitors registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Performance Monitors registers. It does not, and cannot, prevent all accidental or malicious damage.
This register is present only when FEAT_PMUv3_EXT32 is implemented. Otherwise, direct accesses to PMLSR are RES0.
If FEAT_DoPD is implemented, Software Lock is not implemented by the architecturally-defined debug components of the PE in the Core power domain.
If FEAT_DoPD is not implemented, this register is in the Debug power domain.
Software uses PMU.PMLAR to set or clear the lock, and PMLSR to check the current status of the lock.
PMLSR is a 32-bit register.
This register is part of the PMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | nTT | SLK | SLI | ||||||||||||||||||||||||||||
Reserved, RES0.
Not thirty-two bit access required.
Reads as 0b0.
Access to this field is RO.
Software Lock status for this component. For an access to LSR that is not a memory-mapped access, or when Software Lock is not implemented, this field is RES0.
For memory-mapped accesses when Software Lock is implemented, possible values of this field are:
| SLK | Meaning |
|---|---|
| 0b0 |
Lock clear. Writes are permitted to this component's registers. |
| 0b1 |
Lock set. Writes to this component's registers are ignored, and reads have no side effects. |
The reset behavior of this field is:
Reserved, RAZ.
Software Lock implemented. For an access to LSR that is not a memory-mapped access, this field is RAZ.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SLI | Meaning |
|---|---|
| 0b0 |
Software Lock not implemented or not memory-mapped access. |
| 0b1 |
Software Lock implemented and memory-mapped access. |
Access to this field is RO.
Accesses to this register use the following encodings:
Accessible at offset 0xFB4 from PMU