PMINTENCLR_EL1 | Jon's Arm Reference

Allows software to disable the generation of interrupt requests or, when FEAT_EBEP is implemented, PMU exceptions on overflows from the following counters:

Reading from this register shows which overflow interrupt requests or PMU exceptions are enabled.

Configuration

External register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch64 System register PMINTENCLR_EL1[31:0] when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is not implemented.

External register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch64 System register PMINTENSET_EL1[31:0] when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is not implemented.

External register PMINTENCLR_EL1 bits [63:0] are architecturally mapped to AArch64 System register PMINTENCLR_EL1[63:0] when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented.

External register PMINTENCLR_EL1 bits [63:0] are architecturally mapped to AArch64 System register PMINTENSET_EL1[63:0] when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented.

External register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PMINTENCLR[31:0].

External register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PMINTENSET[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMINTENCLR_EL1 are RES0.

Attributes

Field descriptions

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented:

Bits [63:33]

F0, bit [32]

When FEAT_PMUv3_ICNTR is implemented:

Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 disable. On writes, allows software to disable the interrupt request on unsigned overflow of PMU.PMICNTR_EL0. On reads, returns the interrupt request on unsigned overflow of PMU.PMICNTR_EL0 enable status.

F0	Meaning
0b0	Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 disabled.
0b1	Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Accessing this field has the following behavior:

When SoftwareLockStatus(), access to this field is RO.
Otherwise, access to this field is W1C.

Otherwise:

C, bit [31]

Interrupt request or PMU exception on unsigned overflow of PMU.PMCCNTR_EL0 disable. On writes, allows software to disable the interrupt request or PMU exception on unsigned overflow of PMU.PMCCNTR_EL0. On reads, returns the interrupt request or PMU exception on unsigned overflow of PMU.PMCCNTR_EL0 enable status.

C	Meaning
0b0	Interrupt request or PMU exception on unsigned overflow of PMU.PMCCNTR_EL0 disabled.
0b1	Interrupt request or PMU exception on unsigned overflow of PMU.PMCCNTR_EL0 enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When SoftwareLockStatus(), access to this field is RO.
Otherwise, access to this field is W1C.

P<m>, bit [m], for m = 30 to 0

Interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m>_EL0 disable. On writes, allows software to disable the interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m>_EL0. On reads, returns the interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m>_EL0 enable status.

P<m>	Meaning
0b0	Interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m>_EL0 disabled.
0b1	Interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m>_EL0 enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When m >= NUM_PMU_COUNTERS, access to this field is RAZ/WI.
When SoftwareLockStatus(), access to this field is RO.
Otherwise, access to this field is W1C.

Otherwise:

C, bit [31]

C	Meaning
0b0	Interrupt request or PMU exception on unsigned overflow of PMU.PMCCNTR_EL0 disabled.
0b1	Interrupt request or PMU exception on unsigned overflow of PMU.PMCCNTR_EL0 enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When SoftwareLockStatus(), access to this field is RO.
Otherwise, access to this field is W1C.

P<m>, bit [m], for m = 30 to 0

P<m>	Meaning
0b0	Interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m>_EL0 disabled.
0b1	Interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m>_EL0 enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When m >= NUM_PMU_COUNTERS, access to this field is RAZ/WI.
When SoftwareLockStatus(), access to this field is RO.
Otherwise, access to this field is W1C.

Accessing PMINTENCLR_EL1

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings:

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3_ICNTR is implemented or FEAT_PMUv3p9 is implemented

[63:0] Accessible at offset 0xC60 from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
When FEAT_PMUv3_EXT32 is implemented and SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

When FEAT_PMUv3_EXT32 is implemented, FEAT_PMUv3_ICNTR is not implemented and FEAT_PMUv3p9 is not implemented

[31:0] Accessible at offset 0xC60 from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
When SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																															F0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

PMINTENCLR_EL1: Performance Monitors Interrupt Enable Clear Register

Purpose

Configuration

Attributes

Field descriptions

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented:

Bits [63:33]

F0, bit [32]

When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]

P<m>, bit [m], for m = 30 to 0

Otherwise:

C, bit [31]

P<m>, bit [m], for m = 30 to 0

Accessing PMINTENCLR_EL1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

PMINTENCLR_EL1: Performance Monitors Interrupt Enable Clear Register

Purpose

Configuration

Attributes

Field descriptions

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented:

Bits [63:33]

F0, bit [32]When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]

P<m>, bit [m], for m = 30 to 0

Otherwise:

C, bit [31]

P<m>, bit [m], for m = 30 to 0

Accessing PMINTENCLR_EL1

F0, bit [32]

When FEAT_PMUv3_ICNTR is implemented:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0