Provides information about features of the Performance Monitors implementation.
This register is present only when FEAT_PMUv3_EXT32 is implemented. Otherwise, direct accesses to PMDEVID are RES0.
If FEAT_DoPD is implemented, this register is in the Core power domain.
If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required from Armv8.2 and in any implementation that includes FEAT_PCSRv8p2. Otherwise, its location is RES0.
Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
PMDEVID is a 32-bit register.
This register is part of the PMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | PMSS | PCSample | |||||||||||||||||||||||||||||
Reserved, RES0.
PMU Snapshot extension.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| PMSS | Meaning |
|---|---|
| 0b0000 |
PMU snapshot extension not implemented. |
| 0b0001 |
PMU snapshot extension implemented. |
All other values are reserved.
FEAT_PMUv3_SS implements the functionality identified by the value 0b0001.
Access to this field is RO.
Indicates the level of PC Sample-based Profiling support using Performance Monitors registers.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| PCSample | Meaning |
|---|---|
| 0b0000 |
PC Sample-based Profiling Extension is not implemented in the Performance Monitors register space. |
| 0b0001 |
PC Sample-based Profiling Extension is implemented in the Performance Monitors register space. |
| 0b0010 |
As 0b0001, and adds support for PMU.PMPCSCTL. |
All other values are reserved.
FEAT_PCSRv8p2 implements the functionality identified by the value 0b0001.
FEAT_PCSRv8p9 implements the functionality identified by the value 0b0010.
If FEAT_PCSRv8p2 is not implemented, then the only permitted value is 0b0000.
From Armv8.2, when FEAT_PCSRv8p2 is implemented, the value 0b0000 is not permitted.
From Armv8.9, when FEAT_PCSRv8p9 is implemented, the value 0b0001 is not permitted.
Access to this field is RO.
Accesses to this register use the following encodings:
Accessible at offset 0xFC8 from PMU