Provides information to identify a Performance Monitor component.
For more information, see 'About the Component Identification scheme'.
This register is present only when FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR2. Otherwise, direct accesses to PMCIDR2 are RES0.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMCIDR2 is a 32-bit register.
This register is part of the PMU block.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_2 |
Reserved, RES0.
Preamble.
Reads as 0x05.
Access to this field is RO.
Accesses to this register use the following encodings:
Accessible at offset 0xFF8 from PMU