Contains the sampled value of CONTEXTIDR_EL2, captured on reading PMU.PMPCSR[31:0].
This register is present only when FEAT_PMUv3_EXT32 is implemented. Otherwise, direct accesses to PMCID2SR are RES0.
If FEAT_PMUv3_EXT64 is implemented, the same content is present in the same location, and can be accessed using PMCCIDSR[63:32].
PMCIDR2SR is in the Core power domain.
If FEAT_PCSRv8p2 is not implemented, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
PMCID2SR is a 32-bit register.
This register is part of the PMU block.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTEXTIDR_EL2 |
Context ID. The value of CONTEXTIDR_EL2 that is associated with the most recent PMU.PMPCSR sample. When the most recent PMU.PMPCSR sample is generated:
Because the value written to this field is an indirect read of CONTEXTIDR_EL2, it is CONSTRAINED UNPREDICTABLE whether this field is set to the original or new value if PMU.PMPCSR samples:
The reset behavior of this field is:
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
Accesses to this register use the following encodings:
Accessible at offset 0x22C from PMU