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PMCEID2: Performance Monitors Common Event Identification register 2

Purpose

Defines which Common architectural events and Common microarchitectural events are implemented, or counted, using PMU events in the range 0x4000 to 0x401F.

For more information about the Common events and the use of the PMCEIDn registers, see 'The PMU event number space and common events'.

Configuration

External register PMCEID2 bits [31:0] are architecturally mapped to AArch64 System register PMCEID0_EL0[63:32].

External register PMCEID2 bits [31:0] are architecturally mapped to AArch32 System register PMCEID2[31:0].

This register is present only when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p1 is implemented. Otherwise, direct accesses to PMCEID2 are RES0.

PMCEID2 is in the Core power domain.

Attributes

PMCEID2 is a 32-bit register.

This register is part of the PMU block.

Field descriptions

313029282726252423222120191817161514131211109876543210
IDhi31IDhi30IDhi29IDhi28IDhi27IDhi26IDhi25IDhi24IDhi23IDhi22IDhi21IDhi20IDhi19IDhi18IDhi17IDhi16IDhi15IDhi14IDhi13IDhi12IDhi11IDhi10IDhi9IDhi8IDhi7IDhi6IDhi5IDhi4IDhi3IDhi2IDhi1IDhi0

IDhi<n>, bit [n], for n = 31 to 0

IDhi[n] corresponds to Common event (0x4000 + n).

For each bit:

IDhi<n>Meaning
0b0

The Common event is not implemented, or not counted.

0b1

The Common event is implemented.

When the value of a bit in the field is 1, the corresponding Common event is implemented and counted.

Note

Arm recommends that if a Common event is never counted, the value of the corresponding bit is 0.

A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional Common event.

Note

Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n> registers of that earlier version of the PMU architecture.

Accessing PMCEID2

Note

AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings:

Accessible at offset 0xE28 from PMU