Defines which Common architectural events and Common microarchitectural events are implemented, or counted, using PMU events in the range 0x0000 to 0x001F.
For more information about the Common events and the use of the PMCEIDn registers, see 'The PMU event number space and common events'.
This view of the register was previously called PMCEID0_EL0.
External register PMCEID0 bits [31:0] are architecturally mapped to AArch64 System register PMCEID0_EL0[31:0].
External register PMCEID0 bits [31:0] are architecturally mapped to AArch32 System register PMCEID0[31:0].
This register is present only when FEAT_PMUv3_EXT32 is implemented. Otherwise, direct accesses to PMCEID0 are RES0.
PMCEID0 is in the Core power domain.
PMCEID0 is a 32-bit register.
This register is part of the PMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ID31 | ID30 | ID29 | ID28 | ID27 | ID26 | ID25 | ID24 | ID23 | ID22 | ID21 | ID20 | ID19 | ID18 | ID17 | ID16 | ID15 | ID14 | ID13 | ID12 | ID11 | ID10 | ID9 | ID8 | ID7 | ID6 | ID5 | ID4 | ID3 | ID2 | ID1 | ID0 |
ID[n] corresponds to Common event n.
For each bit:
| ID<n> | Meaning |
|---|---|
| 0b0 |
The Common event is not implemented, or not counted. |
| 0b1 |
The Common event is implemented. |
When the value of a bit in the field is 1, the corresponding Common event is implemented and counted.
Arm recommends that if a Common event is never counted, the value of the corresponding bit is 0.
A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional Common event.
Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n> registers of that earlier version of the PMU architecture.
AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings:
Accessible at offset 0xE20 from PMU