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PMCCNTR_EL0: Performance Monitors Cycle Counter

Purpose

Holds the value of the processor Cycle Counter, CCNT, that counts processor clock cycles. For more information, see 'Time as measured by the Performance Monitors cycle counter'.

PMU.PMCCFILTR_EL0 determines the modes and states in which the PMCCNTR_EL0 can increment.

Configuration

External register PMCCNTR_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMCCNTR_EL0[63:0].

External register PMCCNTR_EL0 bits [63:0] are architecturally mapped to AArch32 System register PMCCNTR[63:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCCNTR_EL0 are RES0.

PMCCNTR_EL0 is in the Core power domain.

Attributes

PMCCNTR_EL0 is a 64-bit register.

This register is part of the PMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
CCNT
CCNT

CCNT, bits [63:0]

Cycle count. Depending on the values of PMU.PMCR_EL0.{LC,D}, the cycle count increments in one of the following ways:

Writing 1 to PMU.PMCR_EL0.C sets this field to 0.

The reset behavior of this field is:

Accessing PMCCNTR_EL0

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings:

When FEAT_PMUv3_EXT64 is implemented

[63:0] Accessible at offset 0x0F8 from PMU

When FEAT_PMUv3_EXT32 is implemented

[31:0] Accessible at offset 0x0F8 from PMU

When FEAT_PMUv3_EXT32 is implemented

[63:32] Accessible at offset 0x0FC from PMU