TRCTRACEIDR | Jon's Arm Reference

External register TRCTRACEIDR bits [31:0] are architecturally mapped to AArch64 System register TRCTRACEIDR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCTRACEIDR are RES0.

Attributes

Field descriptions

Bits [31:7]

TRACEID, bits [6:0]

Trace ID field. Sets the trace ID value for instruction trace. The width of the field is indicated by the value of TRCIDR5.TRACEIDSIZE. Unimplemented bits are RES0.

If an implementation supports AMBA ATB, then:

The width of the field is 7 bits.
Writing a reserved trace ID value does not affect behavior of the trace unit but it might cause UNPREDICTABLE behavior of the trace capture infrastructure.

See the AMBA ATB Protocol Specification for information about which ATID values are reserved.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing TRCTRACEIDR

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																									TRACEID

TRCTRACEIDR: Trace ID Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:7]

TRACEID, bits [6:0]

Accessing TRCTRACEIDR

TRCTRACEIDR can be accessed through the external debug interface: