Use this to set, or read, the status of the resources.
External register TRCRSR bits [31:0] are architecturally mapped to AArch64 System register TRCRSR[31:0].
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCRSR are RES0.
TRCRSR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | TA | EVENT[3] | EVENT[2] | EVENT[1] | EVENT[0] | RES0 | EXTIN[3] | EXTIN[2] | EXTIN[1] | EXTIN[0] | |||||||||||||||||||||
Reserved, RES0.
Tracing active.
| TA | Meaning |
|---|---|
| 0b0 |
Tracing is not active. |
| 0b1 |
Tracing is active. |
The reset behavior of this field is:
Untraced status of ETEEvents.
| EVENT[<m>] | Meaning |
|---|---|
| 0b0 |
An ETEEvent <m> has not occurred. |
| 0b1 |
An ETEEvent <m> has occurred while the resources were in the Paused state. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
The sticky status of the External Input Selectors.
| EXTIN[<m>] | Meaning |
|---|---|
| 0b0 |
An event selected by External Input Selector <m> has not occurred. |
| 0b1 |
At least one event selected by External Input Selector <m> has occurred while the resources were in the Paused state. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Must always be programmed.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.
| Component | Offset | Instance |
|---|---|---|
| ETE | 0x028 | TRCRSR |
This interface is accessible as follows: