Returns the tracing capabilities of the trace unit.
External register TRCIDR6 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR6[31:0].
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCIDR6 are RES0.
TRCIDR6 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | EXLEVEL_RL_EL2 | EXLEVEL_RL_EL1 | EXLEVEL_RL_EL0 | ||||||||||||||||||||||||||||
Reserved, RES0.
Indicates if Realm EL2 is implemented.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EXLEVEL_RL_EL2 | Meaning |
|---|---|
| 0b0 |
Realm EL2 is not implemented. |
| 0b1 |
Realm EL2 is implemented. |
Access to this field is RO.
Indicates if Realm EL1 is implemented.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EXLEVEL_RL_EL1 | Meaning |
|---|---|
| 0b0 |
Realm EL1 is not implemented. |
| 0b1 |
Realm EL1 is implemented. |
Access to this field is RO.
Indicates if Realm EL0 is implemented.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EXLEVEL_RL_EL0 | Meaning |
|---|---|
| 0b0 |
Realm EL0 is not implemented. |
| 0b1 |
Realm EL0 is implemented. |
Access to this field is RO.
| Component | Offset | Instance |
|---|---|---|
| ETE | 0x1F8 | TRCIDR6 |
This interface is accessible as follows: