In conjunction with TRCCLAIMSET, provides Claim Tag bits that can be separately set and cleared to indicate whether functionality is in use by a debug agent.
For additional information, see the CoreSight Architecture Specification.
External register TRCCLAIMCLR bits [31:0] are architecturally mapped to AArch64 System register TRCCLAIMCLR[31:0].
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCCLAIMCLR are RES0.
TRCCLAIMCLR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLR[31] | CLR[30] | CLR[29] | CLR[28] | CLR[27] | CLR[26] | CLR[25] | CLR[24] | CLR[23] | CLR[22] | CLR[21] | CLR[20] | CLR[19] | CLR[18] | CLR[17] | CLR[16] | CLR[15] | CLR[14] | CLR[13] | CLR[12] | CLR[11] | CLR[10] | CLR[9] | CLR[8] | CLR[7] | CLR[6] | CLR[5] | CLR[4] | CLR[3] | CLR[2] | CLR[1] | CLR[0] |
Claim Tag Clear. Indicates the current status of Claim Tag bit <m>, and is used to clear Claim Tag bit <m> to 0.
| CLR[<m>] | Meaning |
|---|---|
| 0b0 | On a read: Claim Tag bit <m> is not set. On a write: Ignored. |
| 0b1 | On a read: Claim Tag bit <m> is set. On a write: Clear Claim tag bit <m> to 0. |
The number of Claim Tag bits implemented is indicated in TRCCLAIMSET.
This bit reads-as-zero and ignores writes if m > the number of Claim Tag bits.
The reset behavior of this field is:
Access to this field is W1C.
| Component | Offset | Instance |
|---|---|---|
| ETE | 0xFA4 | TRCCLAIMCLR |
This interface is accessible as follows: