Set the threshold value for cycle counting.
External register TRCCCCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCCCCTLR[31:0].
This register is present only when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented and TRCIDR0.TRCCCI == 1. Otherwise, direct accesses to TRCCCCTLR are RES0.
TRCCCCTLR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | THRESHOLD | ||||||||||||||||||||||||||||||
Reserved, RES0.
Sets the threshold value for instruction trace cycle counting.
The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN. If the THRESHOLD value is smaller than the value in TRCIDR3.CCITMIN then the behavior is CONSTRAINED UNPREDICTABLE. That is, cycle counts might or might not be included in the trace and the cycle count threshold is not known.
Writing a value of zero when TRCCONFIGR.CCI enables instruction trace cycle counting results in CONSTRAINED UNPREDICTABLE behavior. That is, cycle counts might or might not be included in the trace and the cycle count threshold is not known.
The reset behavior of this field is:
Must be programmed if TRCCONFIGR.CCI == 1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
| Component | Offset | Instance |
|---|---|---|
| ETE | 0x038 | TRCCCCTLR |
This interface is accessible as follows: