Specifies the number of bytes of trace to capture following a Detected Trigger before a Trigger Event.
External register TRBTRG_EL1 bits [63:0] are architecturally mapped to AArch64 System register TRBTRG_EL1[63:0].
TRBTRG_EL1 is in the Core power domain.
This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBTRG_EL1 are RES0.
TRBTRG_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
TRG |
Reserved, RES0.
Trigger count.
Specifies the number of bytes of trace to capture following a Detected Trigger before a Trigger Event.
TRBTRG_EL1 decrements by 1 for every byte of trace written to the trace buffer when all of the following are true:
The architecture places restrictions on the values that software can write to the counter.
As a result of the restrictions an implementation might treat some of TRG[M:0] as RES0, where M is defined by TRBIDR_EL1.Align.
The reset behavior of this field is:
The PE might ignore a write to TRBTRG_EL1 if any of the following apply:
Component | Offset | Instance |
---|---|---|
TRBE | 0x020 | TRBTRG_EL1 |
This interface is accessible as follows: