← Home

TRBLIMITR_EL1: Trace Buffer Limit Address Register

Purpose

Defines the top address for the trace buffer, and controls the trace buffer modes and enable.

Configuration

External register TRBLIMITR_EL1 bits [63:0] are architecturally mapped to AArch64 System register TRBLIMITR_EL1[63:0].

TRBLIMITR_EL1 is in the Core power domain.

This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBLIMITR_EL1 are RES0.

Attributes

TRBLIMITR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
LIMIT
LIMITRES0XEnVMTMFME

LIMIT, bits [63:12]

Trace buffer Limit pointer address. (TRBLIMITR_EL1.LIMIT << 12) is the address of the last byte in the trace buffer plus one. Bits [11:0] of the Limit pointer address are always zero. If the smallest implemented translation granule is not 4KB, then TRBLIMITR_EL1[N-1:12] are RES0, where N is the IMPLEMENTATION DEFINED value Log2(smallest implemented translation granule).

The reset behavior of this field is:

Bits [11:7]

Reserved, RES0.

XE, bit [6]

Trace Buffer Unit External mode enable. Controls whether the Trace Buffer Unit is enabled when SelfHostedTraceEnabled() == FALSE.

XEMeaning
0b0

Trace Buffer Unit is not enabled by this control.

0b1

If SelfHostedTraceEnabled() is FALSE, the Trace Buffer Unit is enabled.

If SelfHostedTraceEnabled() == TRUE, then TRBLIMITR_EL1.E controls whether the Trace Buffer Unit is enabled.

All output is discarded by the Trace Buffer Unit when the Trace Buffer Unit is disabled.

The reset behavior of this field is:

nVM, bit [5]

Address mode.

nVMMeaning
0b0

The trace buffer pointers are virtual addresses.

0b1

The trace buffer pointers are:

  • Physical address in the owning security state if the owning translation regime has no stage 2 translation.
  • Intermediate physical addresses in the owning security state if the owning translation regime has stage 2 translations.

When SelfHostedTraceEnabled() == FALSE, the trace buffer pointers are always physical addresses.

The reset behavior of this field is:

Accessing this field has the following behavior:

TM, bits [4:3]

Trigger mode.

TMMeaning
0b00

Stop on trigger. Flush trace, then stop collection and set TRBSR_EL1.IRQ to 1 on Trigger Event.

0b01

IRQ on trigger. Continue collection and set TRBSR_EL1.IRQ to 1 on Trigger Event.

0b11

Ignore trigger. Continue collection and leave TRBSR_EL1.IRQ unchanged on Trigger Event.

All other values are reserved.

The reset behavior of this field is:

FM, bits [2:1]

Trace buffer mode.

FMMeaning
0b00

Fill mode. Stop collection and set TRBSR_EL1.IRQ to 1 on current write pointer wrap.

0b01

Wrap mode. Continue collection and set TRBSR_EL1.IRQ to 1 on current write pointer wrap.

0b11

Circular Buffer mode. Continue collection and leave TRBSR_EL1.IRQ unchanged on current write pointer wrap.

All other values are reserved.

The reset behavior of this field is:

E, bit [0]

Trace Buffer Unit enable. Controls whether the Trace Buffer Unit is enabled when SelfHostedTraceEnabled() == TRUE.

EMeaning
0b0

Trace Buffer Unit is not enabled by this control.

0b1

If SelfHostedTraceEnabled() is TRUE, the Trace Buffer Unit is enabled.

If FEAT_TRBE_EXT is implemented and SelfHostedTraceEnabled() == FALSE, then TRBLIMITR_EL1.XE controls whether the Trace Buffer Unit is enabled.

If FEAT_TRBE_EXT is not implemented, then the Trace Buffer Unit is disabled when SelfHostedTraceEnabled() == FALSE.

All output is discarded by the Trace Buffer Unit when the Trace Buffer Unit is disabled.

The reset behavior of this field is:

Accessing TRBLIMITR_EL1

The PE might ignore a write to TRBLIMITR_EL1, other than a write that modifies TRBLIMITR_EL1.E or TRBLIMITR_EL1.XE as appropriate, if any of the following apply:

TRBLIMITR_EL1 can be accessed through the external debug interface:

ComponentOffsetInstance
TRBE0x010TRBLIMITR_EL1

This interface is accessible as follows: