Describes constraints on using the Trace Buffer Unit to an external debugger.
External register TRBIDR_EL1 bits [63:0] are architecturally mapped to AArch64 System register TRBIDR_EL1[63:0].
TRBIDR_EL1 is in the Core power domain.
This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBIDR_EL1 are RES0.
TRBIDR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | EA | RES0 | F | P | Align | ||||||||||||||||||||||||||
Reserved, RES0.
External Abort handling. Describes how the PE manages External aborts on writes made by the Trace Buffer Unit to the trace buffer.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EA | Meaning |
|---|---|
| 0b0001 |
The PE ignores External aborts on writes made by the Trace Buffer Unit. |
| 0b0010 |
The External abort generates an asynchronous SError exception at the PE. |
All other values are reserved.
Access to this field is RO.
Reserved, RES0.
Reserved, RES0.
Flag updates. Describes how address translations performed by the Trace Buffer Unit manage the Access flag and dirty state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F | Meaning |
|---|---|
| 0b0 |
Hardware management of the Access flag and dirty state for accesses made by the Trace Buffer Unit is always disabled for all translation stages. |
| 0b1 |
Hardware management of the Access flag and dirty state for accesses made by the Trace Buffer Unit is controlled in the same way as explicit memory accesses in the trace buffer owning translation regime. |
If hardware management of the Access flag is disabled for a stage of translation, an access to a Page or Block with the Access flag bit not set in the descriptor will generate an Access Flag fault.
If hardware management of the dirty state is disabled for a stage of translation, an access to a Page or Block will ignore the Dirty Bit Modifier in the descriptor and might generate a Permission fault, depending on the values of the access permission bits in the descriptor.
From Armv9.3, the value 0b0 is not permitted.
Access to this field is RO.
This field reads as an UNKNOWN value.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Align | Meaning |
|---|---|
| 0b0000 |
Byte. |
| 0b0001 |
Halfword. |
| 0b0010 |
Word. |
| 0b0011 |
Doubleword. |
| 0b0100 |
16 bytes. |
| 0b0101 |
32 bytes. |
| 0b0110 |
64 bytes. |
| 0b0111 |
128 bytes. |
| 0b1000 |
256 bytes. |
| 0b1001 |
512 bytes. |
| 0b1010 |
1KB. |
| 0b1011 |
2KB. |
All other values are reserved.
Access to this field is RO.
| Component | Offset | Instance |
|---|---|---|
| TRBE | 0x030 | TRBIDR_EL1 |
This interface is accessible as follows: