Shows the status for the records in the group.
ERRGSR is implemented only as part of a memory-mapped group of error records.
This manual describes a group of error records accessed via a standard 4KB memory-mapped peripheral. For a 4KB peripheral, up to 24 error records can be accessed if the Common Fault Injection Model is implemented, and up to 56 otherwise.
ERRGSR is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | S55 | S54 | S53 | S52 | S51 | S50 | S49 | S48 | S47 | S46 | S45 | S44 | S43 | S42 | S41 | S40 | S39 | S38 | S37 | S36 | S35 | S34 | S33 | S32 | |||||||
S31 | S30 | S29 | S28 | S27 | S26 | S25 | S24 | S23 | S22 | S21 | S20 | S19 | S18 | S17 | S16 | S15 | S14 | S13 | S12 | S11 | S10 | S9 | S8 | S7 | S6 | S5 | S4 | S3 | S2 | S1 | S0 |
Reserved, RES0.
The status for error record <m>. A read-only copy of ERR<m>STATUS.V.
S<m> | Meaning |
---|---|
0b0 |
No error. |
0b1 |
One or more errors. |
If the Common Fault Injection Model is implemented then up-to 24 records can be implemented meaning bits [55:24] are RES0.
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
RAS | 0xE00 | ERRGSR |
Accesses on this interface are RO.