Holds a data address value for use in watchpoint matching. Forms watchpoint n together with control register DBGWCR<n>_EL1.
External register DBGWVR<n>_EL1 bits [63:0] are architecturally mapped to AArch64 System register DBGWVR<n>_EL1[63:0].
External register DBGWVR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGWVR<n>[31:0].
DBGWVR<n>_EL1 is in the Core power domain.
If watchpoint n is not implemented then accesses to this register are:
DBGWVR<n>_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESS[14:8] | Bits[56:53] | Bits[52:49] | VA[48:2] | ||||||||||||||||||||||||||||
VA[48:2] | RES0 |
Reserved, Sign extended. Hardware and software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1.
Hardware always ignores the value of these bits and it is IMPLEMENTATION DEFINED whether:
Extension to VA[48:2]. For more information, see VA[48:2].
The reset behavior of this field is:
Extension to RESS[14:8]. For more information, see RESS[14:8].
Extension to VA[48:2]. For more information, see VA[48:2].
The reset behavior of this field is:
Extension to RESS[14:8]. For more information, see RESS[14:8].
Bits[48:2] of the address value for comparison.
When FEAT_LVA3 is implemented, (VA[56:53]:VA[52:49]) forms the upper part of the address value. If FEAT_LVA3 is not implemented, bits VA[56:53] are part of the RESS field.
When FEAT_LVA is implemented, VA[52:49] forms the upper part of the address value. If FEAT_LVA is not implemented, bits [52:49] are part of the RESS field.
Arm deprecates setting DBGWVR<n>_EL1[2] == 1.
The reset behavior of this field is:
Reserved, RES0.
SoftwareLockStatus() depends on the type of access attempted and AllowExternalDebugAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Component | Offset | Instance | Range |
---|---|---|---|
Debug | 0x800 + (16 * n) | DBGWVR<n>_EL1 | 63:0 |
This interface is accessible as follows: