Enable control bits for the auxiliary activity monitors event counters, AMU.AMEVCNTR1<n>.
External register AMCNTENSET1 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENCLR1_EL0[31:0].
External register AMCNTENSET1 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENSET1_EL0[31:0].
External register AMCNTENSET1 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENCLR1[31:0].
External register AMCNTENSET1 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENSET1[31:0].
It is IMPLEMENTATION DEFINED whether AMCNTENSET1 is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented and FEAT_AMU_EXT32 is implemented. Otherwise, direct accesses to AMCNTENSET1 are RES0.
AMCNTENSET1 is a 32-bit register.
This register is part of the AMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 | |||||||||||||||
Reserved, RES0.
Activity monitor event counter enable bit for AMU.AMEVCNTR1<n>.
When N is less than 16, bits [15:N] are RAZ, where N is the value in AMU.AMCGCR.CG1NC.
Possible values of each bit are:
| P<n> | Meaning |
|---|---|
| 0b0 |
When read, means that AMU.AMEVCNTR1<n> is disabled. |
| 0b1 |
When read, means that AMU.AMEVCNTR1<n> is enabled. |
The reset behavior of this field is:
If there are no auxiliary monitor event counters implemented, reads of AMCNTENSET1 are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.
There are no implemented auxiliary activity monitor event counters when AMU.AMCFGR.NCG == 0b0000.
Accesses to this register use the following encodings:
Accessible at offset 0xC04 from AMU
Accesses on this interface are RO.