Enable control bits for the architected activity monitors event counters, AMU.AMEVCNTR0<n>.
External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENCLR0_EL0[31:0].
External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENSET0_EL0[31:0].
External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENCLR0[31:0].
External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENSET0[31:0].
It is IMPLEMENTATION DEFINED whether AMCNTENSET0 is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented and FEAT_AMU_EXT32 is implemented. Otherwise, direct accesses to AMCNTENSET0 are RES0.
AMCNTENSET0 is a 32-bit register.
This register is part of the AMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | RAZ/WI | P3 | P2 | P1 | P0 | ||||||||||||||||||||||||||
Reserved, RES0.
Reserved, RAZ/WI.
This field is reserved for additional architected activity monitor event counters, which Arm might define in a future version of the Activity Monitors architecture.
Activity monitor event counter enable bit for AMU.AMEVCNTR0<n>.
AMU.AMCGCR.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.
Possible values of each bit are:
| P<n> | Meaning |
|---|---|
| 0b0 |
When read, means that AMU.AMEVCNTR0<n> is disabled. |
| 0b1 |
When read, means that AMU.AMEVCNTR0<n> is enabled. |
The reset behavior of this field is:
Accesses to this register use the following encodings:
Accessible at offset 0xC00 from AMU
Accesses on this interface are RO.