Disable control bits for the architected and auxiliary activity monitors event counters, AMU.AMEVCNTR0<n> and AMU.AMEVCNTR1<n>.
External register AMCNTENCLR bits [31:0] are architecturally mapped to AArch64 System register AMCNTENCLR0_EL0[31:0].
External register AMCNTENCLR bits [63:32] are architecturally mapped to AArch64 System register AMCNTENCLR1_EL0[31:0].
It is IMPLEMENTATION DEFINED whether AMCNTENCLR is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented and FEAT_AMU_EXT64 is implemented. Otherwise, direct accesses to AMCNTENCLR are RES0.
AMCNTENCLR is a 64-bit register.
This register is part of the AMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | P115 | P114 | P113 | P112 | P111 | P110 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | |||||||||||||||
| RES0 | RAZ/WI | P03 | P02 | P01 | P00 | ||||||||||||||||||||||||||
Reserved, RES0.
Activity monitor event counter disable bit for AMU.AMEVCNTR1<n>.
When N is less than 16, bits [15:N] are RAZ, where N is the value in AMU.AMCGCR.CG1NC.
Possible values of each bit are:
| P1<n> | Meaning |
|---|---|
| 0b0 |
When read, means that AMU.AMEVCNTR1<n> is disabled. |
| 0b1 |
When read, means that AMU.AMEVCNTR1<n> is enabled. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RAZ/WI.
This field is reserved for additional architected activity monitor event counters, which Arm might define in a future version of the Activity Monitors architecture.
Activity monitor event counter disable bit for AMU.AMEVCNTR0<n>.
AMU.AMCGCR.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.
Possible values of each bit are:
| P0<n> | Meaning |
|---|---|
| 0b0 |
When read, means that AMU.AMEVCNTR0<n> is disabled. |
| 0b1 |
When read, means that AMU.AMEVCNTR0<n> is enabled. |
The reset behavior of this field is:
If there are no auxiliary monitor event counters implemented, reads of AMCNTENCLR[63:32] are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.
There are no implemented auxiliary activity monitor event counters when AMU.AMCFGR.NCG == 0b0000.
Accesses to this register use the following encodings:
Accessible at offset 0xC20 from AMU
Accesses on this interface are RO.