Provides information to identify an activity monitors component.
For more information, see 'About the Component identification scheme'.
It is IMPLEMENTATION DEFINED whether AMCIDR2 is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented and an implementation implements AMCIDR2. Otherwise, direct accesses to AMCIDR2 are RES0.
AMCIDR2 is a 32-bit register.
This register is part of the AMU block.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_2 |
Reserved, RES0.
Preamble.
Reads as 0x05.
Access to this field is RO.
Accesses to this register use the following encodings:
Accessible at offset 0xFF8 from AMU
Accesses on this interface are RO.