AMCIDR0: Activity Monitors Component Identification Register 0

Purpose

Provides information to identify an activity monitors component.

For more information, see 'About the Component identification scheme'.

Configuration

It is IMPLEMENTATION DEFINED whether AMCIDR0 is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented and an implementation implements AMCIDR0. Otherwise, direct accesses to AMCIDR0 are RES0.

Attributes

AMCIDR0 is a 32-bit register.

This register is part of the AMU block.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								PRMBL_0

Bits [31:8]

Reserved, RES0.

PRMBL_0, bits [7:0]

Preamble.

Reads as 0x0D.

Access to this field is RO.

Accessing AMCIDR0

Accesses to this register use the following encodings:

Accessible at offset 0xFF0 from AMU

Accesses on this interface are RO.