Provides information on the number of activity monitor event counters implemented within each counter group.
External register AMCGCR bits [31:0] are architecturally mapped to AArch64 System register AMCGCR_EL0[31:0] when FEAT_AMU_EXT32 is implemented.
External register AMCGCR bits [63:0] are architecturally mapped to AArch64 System register AMCGCR_EL0[63:0] when FEAT_AMU_EXT64 is implemented.
External register AMCGCR bits [31:0] are architecturally mapped to AArch32 System register AMCGCR[31:0].
It is IMPLEMENTATION DEFINED whether AMCGCR is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCGCR are RES0.
AMCGCR is a:
This register is part of the AMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | CG1NC | CG0NC | |||||||||||||||||||||||||||||
Reserved, RES0.
Counter Group 1 Number of Counters. The number of counters in the auxiliary counter group.
In an implementation that includes FEAT_AMUv1, the permitted range of values is 0 to 16.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Counter Group 0 Number of Counters. The number of counters in the architected counter group.
Reads as 0x04.
Access to this field is RO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | CG1NC | CG0NC | |||||||||||||||||||||||||||||
Reserved, RES0.
Counter Group 1 Number of Counters. The number of counters in the auxiliary counter group.
In an implementation that includes FEAT_AMUv1, the permitted range of values is 0 to 16.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Counter Group 0 Number of Counters. The number of counters in the architected counter group.
Reads as 0x04.
Access to this field is RO.
Accesses to this register use the following encodings:
When FEAT_AMU_EXT64 is implementedAccessible at offset 0xCE0 from AMU
Accesses on this interface are RO.
Accessible at offset 0xCE0 from AMU
Accesses on this interface are RO.