Global configuration register for the activity monitors.
Provides information on supported features, the number of counter groups implemented, the total number of activity monitor event counters implemented, and the size of the counters. AMCFGR is applicable to both the architected and the auxiliary counter groups.
External register AMCFGR bits [31:0] are architecturally mapped to AArch64 System register AMCFGR_EL0[31:0] when FEAT_AMU_EXT32 is implemented.
External register AMCFGR bits [63:0] are architecturally mapped to AArch64 System register AMCFGR_EL0[63:0] when FEAT_AMU_EXT64 is implemented.
External register AMCFGR bits [31:0] are architecturally mapped to AArch32 System register AMCFGR[31:0].
It is IMPLEMENTATION DEFINED whether AMCFGR is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCFGR are RES0.
AMCFGR is a:
This register is part of the AMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| NCG | RES0 | HDBG | RAZ | SIZE | N | ||||||||||||||||||||||||||
Reserved, RES0.
Defines the number of counter groups implemented, minus one.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NCG | Meaning |
|---|---|
| 0b0000 |
One counter group implemented. |
| 0b0001 |
Two counter groups implemented. |
All other values are reserved.
Access to this field is RO.
Reserved, RES0.
Halt-on-debug supported.
This feature must be supported, and so this bit is 0b1.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HDBG | Meaning |
|---|---|
| 0b0 |
AMU.AMCR.HDBG is RES0. |
| 0b1 |
AMU.AMCR.HDBG is read/write. |
Access to this field is RO.
Reserved, RAZ.
Defines the size of the activity monitor event counters, minus one.
The counters are 64-bit, so the value of this field is 0b111111.
This field is used by software to determine the spacing of the counters in the memory-map. The counters are at doubleword-aligned addresses.
Reads as 0b111111.
Access to this field is RO.
Defines the number of activity monitor event counters implemented in all groups, minus one.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NCG | RES0 | HDBG | RAZ | SIZE | N | ||||||||||||||||||||||||||
Defines the number of counter groups implemented, minus one.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NCG | Meaning |
|---|---|
| 0b0000 |
One counter group implemented. |
| 0b0001 |
Two counter groups implemented. |
All other values are reserved.
Access to this field is RO.
Reserved, RES0.
Halt-on-debug supported.
This feature must be supported, and so this bit is 0b1.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HDBG | Meaning |
|---|---|
| 0b0 |
AMU.AMCR.HDBG is RES0. |
| 0b1 |
AMU.AMCR.HDBG is read/write. |
Access to this field is RO.
Reserved, RAZ.
Defines the size of the activity monitor event counters, minus one.
The counters are 64-bit, so the value of this field is 0b111111.
This field is used by software to determine the spacing of the counters in the memory-map. The counters are at doubleword-aligned addresses.
Reads as 0b111111.
Access to this field is RO.
Defines the number of activity monitor event counters implemented in all groups, minus one.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings:
When FEAT_AMU_EXT64 is implementedAccessible at offset 0xE00 from AMU
Accesses on this interface are RO.
Accessible at offset 0xE00 from AMU
Accesses on this interface are RO.