This register controls aspects of SVE visible at Exception levels EL1 and EL0.
This register is present only when FEAT_SVE is implemented. Otherwise, direct accesses to ZCR_EL1 are UNDEFINED.
This register has no effect when FEAT_SME is implemented and the PE is in Streaming SVE mode.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this register has no effect on execution at EL0.
ZCR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | RAZ/WI | LEN | |||||||||||||||||||||||||||||
Reserved, RES0.
Reserved, RAZ/WI.
Requests an Effective Non-streaming SVE vector length at EL1 of (LEN+1)*128 bits. This field also defines the Effective Non-streaming SVE vector length at EL0 when EL2 is not implemented, or EL2 is not enabled in the current Security state, or the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}.
The Non-streaming SVE vector length can be any power of two from 128 bits to 2048 bits inclusive. An implementation can support a subset of the architecturally permitted lengths. An implementation is required to support all lengths that are powers of two, from 128 bits up to its maximum implemented Non-streaming SVE vector length.
When FEAT_SME is not implemented, or the PE is not in Streaming SVE mode, the Effective SVE vector length (VL) is equal to the Effective Non-streaming SVE vector length.
When FEAT_SME is implemented and the PE is in Streaming SVE mode, VL is equal to the Effective Streaming SVE vector length. See SMCR_EL1.
For all purposes other than returning the result of a direct read of ZCR_EL1, the PE selects the Effective Non-streaming SVE vector length by performing checks in the following order:
If EL2 is implemented and enabled in the current Security state, and the requested length is greater than the Effective length at EL2, then the Effective length at EL2 is used.
If EL3 is implemented and the requested length is greater than the Effective length at EL3, then the Effective length at EL3 is used.
Otherwise, the Effective length is the highest supported Non-streaming SVE vector length that is less than or equal to the requested length.
An indirect read of ZCR_EL1.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic ZCR_EL1 or ZCR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ZCR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0001 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.EZ == '0' then UNDEFINED; elsif CPACR_EL1.ZEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x19); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif ELIsInHost(EL2) && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && CPTR_EL3.EZ == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x19); elsif EffectiveHCR_EL2_NVx() == '111' then X[t, 64] = NVMem[0x1E0]; else X[t, 64] = ZCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.EZ == '0' then UNDEFINED; elsif !ELIsInHost(EL2) && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif ELIsInHost(EL2) && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && CPTR_EL3.EZ == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x19); elsif ELIsInHost(EL2) then X[t, 64] = ZCR_EL2; else X[t, 64] = ZCR_EL1; elsif PSTATE.EL == EL3 then if CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else X[t, 64] = ZCR_EL1;
MSR ZCR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0001 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.EZ == '0' then UNDEFINED; elsif CPACR_EL1.ZEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x19); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif ELIsInHost(EL2) && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && CPTR_EL3.EZ == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x19); elsif EffectiveHCR_EL2_NVx() == '111' then NVMem[0x1E0] = X[t, 64]; else ZCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.EZ == '0' then UNDEFINED; elsif !ELIsInHost(EL2) && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif ELIsInHost(EL2) && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && CPTR_EL3.EZ == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x19); elsif ELIsInHost(EL2) then ZCR_EL2 = X[t, 64]; else ZCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then if CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else ZCR_EL1 = X[t, 64];
MRS <Xt>, ZCR_EL12
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b101 | 0b0001 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x1E0]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.EZ == '0' then UNDEFINED; elsif CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && CPTR_EL3.EZ == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x19); else X[t, 64] = ZCR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then if CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else X[t, 64] = ZCR_EL1; else UNDEFINED;
MSR ZCR_EL12, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b101 | 0b0001 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x1E0] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.EZ == '0' then UNDEFINED; elsif CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && CPTR_EL3.EZ == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x19); else ZCR_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then if CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else ZCR_EL1 = X[t, 64]; else UNDEFINED;