Holds the value of the Virtualization Multiprocessor ID. This is the value returned by EL1 reads of MPIDR_EL1.
AArch64 System register VMPIDR_EL2 bits [31:0] are architecturally mapped to AArch32 System register VMPIDR[31:0].
If EL2 is not implemented, reads of this register return the value of the MPIDR_EL1 and writes to the register are ignored.
This register has no effect if EL2 is not enabled in the current Security state.
VMPIDR_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | Aff3 | ||||||||||||||||||||||||||||||
| RES1 | U | RES0 | MT | Aff2 | Aff1 | Aff0 | |||||||||||||||||||||||||
Reserved, RES0.
Affinity level 3. See the description of VMPIDR_EL2.Aff0 for more information.
Aff3 is not supported in AArch32 state.
The reset behavior of this field is:
Reserved, RES1.
Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system.
| U | Meaning |
|---|---|
| 0b0 |
Processor is part of a multiprocessor system. |
| 0b1 |
Processor is part of a uniprocessor system. |
The reset behavior of this field is:
Reserved, RES0.
Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of VMPIDR_EL2.Aff0 for more information about affinity levels.
| MT | Meaning |
|---|---|
| 0b0 |
Performance of PEs at the lowest affinity level is largely independent. |
| 0b1 |
Performance of PEs at the lowest affinity level is very interdependent. |
The reset behavior of this field is:
Affinity level 2. See the description of VMPIDR_EL2.Aff0 for more information.
The reset behavior of this field is:
Affinity level 1. See the description of VMPIDR_EL2.Aff0 for more information.
The reset behavior of this field is:
Affinity level 0. This is the affinity level that is most significant for determining PE behavior. Higher affinity levels are increasingly less significant in determining PE behavior.
The assigned value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, VMPIDR_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0000 | 0b0000 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x050]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = VMPIDR_EL2; elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then X[t, 64] = MPIDR_EL1; else X[t, 64] = VMPIDR_EL2;
MSR VMPIDR_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0000 | 0b0000 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x050] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then VMPIDR_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then return; else VMPIDR_EL2 = X[t, 64];
MRS <Xt>, MPIDR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0000 | 0b101 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.MPIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() then X[t, 64] = VMPIDR_EL2; else X[t, 64] = MPIDR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = MPIDR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = MPIDR_EL1;